The revolutionary Ultra-High Definition (UHD) video has found its way to diverse rich multimedia applications. HEVC (H.265) standard is proposed as the gateway to increase the compression rate with no loss in video quality. Large integer DCT, with sizes 16x16 and 32x32, is one of the key new features of the H.265 standard. In this paper, we propose a new optimized architecture for integer DCT in HEVC encoder. The proposed architecture is a fully pipelined architecture with optimized adder-widths. Simulation results confirm the high performance of the optimized adder-width design. For 16-DCT, the proposed architecture increases the maximum clock frequency by 42.7% and decreases area by 3.1%. While for 32-DCT, the proposed design increases the maximum clock frequency by 64.8% with cost of increasing area by only 3%.