| publication name | An FPGA architecture for Compressed Sensing of Image Signals |
|---|---|
| Authors | S. Elsayed, M. Elsabrouty, O. Muta, and H. Furukawa |
| year | 2016 |
| keywords | |
| journal | JEC-ECC Conference |
| volume | 4 |
| issue | Not Available |
| pages | Not Available |
| publisher | Not Available |
| Local/International | International |
| Paper Link | Not Available |
| Full paper | download |
| Supplementary materials | Not Available |
Abstract
This paper proposes an FPGA architecture of compressive sensing for image signals. The sensing matrix utilized is scrambled block Hadamard, where only 32x32 RAM is used to save the block matrix, and the multiplication operation is reduced to just additions and subtractions using an accumulator. Random row selection is implemented using Linear Feedback Shift Register (LFSR) technique. The proposed architecture can achieve maximum frequency of 171.6 MHz.