Staff Members - Benha University
An FPGA architecture for Compressed Sensing of Image Signals
JEC-ECC Conference • 2016
Publication Information
Authors
S. Elsayed, M. Elsabrouty, O. Muta, and H. Furukawa
Keywords
Not Available
Journal
JEC-ECC Conference
Publisher
Not Available
Volume
4
Issue
Not Available
Pages
Not Available
publication.type
International
Paper Link
Not Available
Supplementary Materials
Not Available
Abstract
This paper proposes an FPGA architecture of compressive sensing for image signals.
The sensing matrix utilized is scrambled block Hadamard, where only 32x32 RAM is
used to save the block matrix, and the multiplication operation is reduced to just
additions and subtractions using an accumulator. Random row selection is
implemented using Linear Feedback Shift Register (LFSR) technique. The proposed
architecture can achieve maximum frequency of 171.6 MHz.
The sensing matrix utilized is scrambled block Hadamard, where only 32x32 RAM is
used to save the block matrix, and the multiplication operation is reduced to just
additions and subtractions using an accumulator. Random row selection is
implemented using Linear Feedback Shift Register (LFSR) technique. The proposed
architecture can achieve maximum frequency of 171.6 MHz.