Staff Members - Benha University
130nm Low power asynchronous AES core
Conference: Circuits and Systems (ISCAS) • 2017
Publication Information
Authors
N El-meligy; M Amin; E Yahya and Y Ismail
Keywords
Asynchronous circuits;Ciphers;Encryption;Power demand;Protocols;Standards
Journal
Conference: Circuits and Systems (ISCAS)
Publisher
IEEE
Volume
Not Available
Issue
Not Available
Pages
4
publication.type
International
Paper Link
Open Link
Supplementary Materials
Not Available
Abstract
Internet of Things (IoT) devices are always having low power budget and high security demands. This paper describes the design and results of fabricated Advanced Encryption Standard (AES) chip in UMC 130 nm CMOS technology by using Faraday standard cells. The AES core is designed in fully QDI asynchronous circuit style. The core ciphers 128-bit data/key in 300 ns and consumes 5.47 mW.