| publication name | 130nm Low power asynchronous AES core |
|---|---|
| Authors | N El-meligy; M Amin; E Yahya and Y Ismail |
| year | 2017 |
| keywords | Asynchronous circuits;Ciphers;Encryption;Power demand;Protocols;Standards |
| journal | Conference: Circuits and Systems (ISCAS) |
| volume | Not Available |
| issue | Not Available |
| pages | 4 |
| publisher | IEEE |
| Local/International | International |
| Paper Link | http://ieeexplore.ieee.org/document/8050832/?section=abstract |
| Full paper | download |
| Supplementary materials | Not Available |
Abstract
Internet of Things (IoT) devices are always having low power budget and high security demands. This paper describes the design and results of fabricated Advanced Encryption Standard (AES) chip in UMC 130 nm CMOS technology by using Faraday standard cells. The AES core is designed in fully QDI asynchronous circuit style. The core ciphers 128-bit data/key in 300 ns and consumes 5.47 mW.