| publication name | Optimizing and comparing CMOS implementations of the C-element in 65nm technology: self-timed ring case |
|---|---|
| Authors | Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet |
| year | 2011 |
| keywords | |
| journal | |
| volume | Not Available |
| issue | Not Available |
| pages | Not Available |
| publisher | Not Available |
| Local/International | International |
| Paper Link | Not Available |
| Full paper | download |
| Supplementary materials | Not Available |
Abstract
Abstract Self-timed rings are a promising approach for designing high-speed serial links or clock generators. This study focuses on the ring stage components–a C-element and an inverter-and compares the performances of different implementations of this component in terms of speed, power consumption and phase noise. We also proposed a new self-timed ring stage-only composed by a C-element with complementary outputs-which allows us to increase the maximum speed of 25% and reduce the power consumption of 60% at the ...