Abstract: This paper introduces a new methodology for optimizing the performance of
Asynchronous-Linear Pipelines. The method supports all delay types, static and variable
time delays, enabling the designers to optimize their architecture taking into account the
timing information of data dependencies, circuit structure and process variations. The
method not only determines the minimum degree of pipelining necessary to satisfy a given
performance target, but also computes the optimum placement of the pipeline stages to ...