Abstract Asynchronous logic is a hot topic due to its interesting features of power saving, low
noise and robustness to parameters variations. However, its performance analysis is
relatively complex. In fact, the handshaking protocol strongly influences the performance of
the pipelined architectures. This paper introduces verified Standard-Logic schematics for
QDI asynchronous latches and analyzes their characteristics. Buffering capacity and
protocol gain are defined and analyzed. Based on this analysis, reduced performance ...