Fredj A, Ben Abdallah M, Malek J, Azar AT (2016) Fundus Image Denoising Using FPGA Hardware Architecture. Int. J. Computer Applications in Technology, 54 (1), 1-13.
Int. J. of Computer Applications in Technology • 2016
Publication Information
Authors
Not Available
Keywords
SRAD filter; FPGA; field-programmable gate arrays; parallel architecture; retinal fundus images; fundus image denoising; image processing; anisotropic diffusion; retinal images.
Journal
Int. J. of Computer Applications in Technology
Publisher
Inderscience Enterprises Ltd.
Volume
54
Issue
1
Pages
1-13
publication.type
International
Paper Link
Open Link
Supplementary Materials
Not Available
Abstract
Image processing algorithms, implemented in hardware, have recently emerged as the most viable solution for improving the performance of image processing systems. In this paper, a version of an anisotropic diffusion technique is used to reduce noise from retinal images, namely Speckle Reducing Anisotropic Diffusion (SRAD). The SRAD filter can improve images corrupted by multiplicative or additive noise, but it has been the most computationally complex and it has not been suitable for software implementation in real-time processing. In this paper, an efficient Field-Programmable Gate Array (FPGA)-based implementation of the SRAD filter is presented to accelerate the processing time. A comparison of the most used classical suppression filters like Gaussian, Median, Perona and Malik anisotropic diffusion has been carried out. The experimental results reveal a 38× performance improvement over the original MATLAB implementation and a 1.33× performance improvement over the hardware implementation using the Xilinx System Generator tool.
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