Staff Members - Benha University
FPGA implementation of 1000base-x Ethernet physical layer core
International Journal of Engineering & Technology • 2018
Publication Information
Authors
E.S. Abdulaziz, A.Zekry, H.L. Zyed, R.M. Tawfeek
Keywords
Giga Ethernet;virtex6 FPGA;PHY; PCS; PMA;8B/10B Coding; Synchronization; PISO; SIPO.
Journal
International Journal of Engineering & Technology
Publisher
Not Available
Volume
7
Issue
4
Pages
2106-2112
publication.type
International
Paper Link
Not Available
Supplementary Materials
Not Available
Abstract
This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical
coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully
at 1.32 Gb/s, 2.5V supply with reduced power consumption.
coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully
at 1.32 Gb/s, 2.5V supply with reduced power consumption.