This paper proposes an FPGA architecture of compressive sensing for image signals.
The sensing matrix utilized is scrambled block Hadamard, where only 32x32 RAM is
used to save the block matrix, and the multiplication operation is reduced to just
additions and subtractions using an accumulator. Random row selection is
implemented using Linear Feedback Shift Register (LFSR) technique. The proposed
architecture can achieve maximum frequency of 171.6 MHz.