The increasing demand for portable computing has elevated power consumption to be one of the most critical embedded systems
design parameters. In this paper, we present a precise high-level power estimation methodology for the software loaded on a
VLIW processor that is based on a functional level power model. The targeted processor of our approach is the TMS320C6416T
DSP from Texas Instrument.We consider several important issues in our model such as the pipeline stall, inter-instructions effect
and cache misses. The contributions are the following. First, a precise model to estimate the power consumption of the targeted
DSP, while running a software algorithm is proposed. Second, we prove the validation and precision of our model on many typical
algorithms applied in signal and image processing. Third, we further validate the precision of our model on a real application
applied in the video processing field. The power consumption estimated by our model is compared to the physically measured
power consumption, achieving a very low average absolute estimation error of 1.65% and a maximum absolute estimation error of only 3.3%.