Abstract This paper describes a high performance single-chip FPGA implementation of the
new Advanced Encryption Standard (AES) algorithm dealing with 128-bit data/key blocks
and operating in Counter (CTR) mode. Counter mode has a proven-tight security and it
enables the simultaneous processing of multiple blocks without losing the feedback mode
advantages. It also gives the advantage of allowing the use of similar hardware for both
encryption and decryption parts. The proposed architecture is modular. The architecture ...