Over the past decades, the MOSFET has continually been scaled down in
size; typical MOSFET channel lengths were once several micrometres, but
nowadays with the ever increasing need for higher current drive and smaller
sizes MOSFETS, hence cheaper. The scaling down had to come to an end
because of its multiple problems like SCE (Short Channel Eect), so new
technologies had to be introduced to solve this matter. SOI had shown better
behaviour compared to bulk MOSFET as it helps reducing SCE by using a
buried oxide. The most promising nowadays reducing SCE and increasing
the scalability and giving better behaviour like more driving currents and
better sub-threshold slopes are MUG FETS (MUltiple Gating FETS) which
introduce better control of gates over channel hence reduce DIBL, leakage
current and improve the overall performance.
In this thesis we are focusing more on DG MOSFETS(Double Gate) as
The DG-MOSFET seems to be a good candidate to meet the International
Technology Road- map (ITRS-2009) requirements for high-performance logic
technology. so we made simulation analysis of DG mosfets performing in both
high temperature and high frequency to prec=dict how they behave under
those circumstances due to further applications for them in extended Thz
applications.